In a typical quad-data rate system, an internally selected clock signal pair (EC/EC#) is used to output data. That is, the output data is synchronized with the internally selected clock signal pair EC/EC#. The internally selected clock signal pair EC/EC# includes a pair of complementary clock signals, namely, clock signal EC, and complementary clock signal EC#. This terminology is used throughout the present specification. The internally selected clock signal pair EC/EC# is typically selected from either an input clock signal pair K/K# or an output clock signal pair C/C#. Input clock signal pair K/K# typically controls and aligns the timing of the input signals to the system, while output clock signal pair C/C# typically controls and aligns the timing of the output signals from the system. (Thus, ‘output’ clock signals C and C# are actually input signals.)
FIG. 1 is a schematic diagram of a simple circuit 100 for providing either an input clock signal pair K/K# or an output clock signal pair C/C# as the internally selected clock signal pair EC/EC#. Circuit 100 includes logical AND gate 101 and multiplexer 102. AND gate 101 is coupled to receive the output clock signals C and C# of the output clock signal pair C/C#. If the both of the output clock signals C and C# have a logic high state (e.g., are tied to the VDD supply voltage), then AND gate 101 will provide a clock pulse signal CPULSE having a logic “1” state. Otherwise, the clock pulse signal CPULSE has a logic “0” state.
The clock pulse signal CPULSE is applied to the control terminal of multiplexer 102. If the clock pulse signal CPULSE signal has a logic ‘1’ state, then multiplexer 102 routes the input clock signal pair K/K# as the internally selected clock signal pair EC/EC#. Conversely, if the clock pulse signal CPULSE has a logic ‘0’ state, then multiplexer 102 routes the output clock signal pair C/C# as the internally selected clock signal pair EC/EC#.
The internally selected clock signal pair EC/EC# is provided to data output circuit 103. In response, data output circuit 103 transfers received data values DI as output data values DO. In a typical high speed application, the data output circuit 103 includes a delay locked loop (DLL), which aligns the output data values DO to the internally selected clock signal pair EC/EC#.
FIG. 2 is a waveform diagram illustrating conventional output clock signals C and C#. The output clock signal pair C/C# (and the input clock signal pair K/K#) must conform to certain specifications. For example, each of the output clock signals C and C# typically requires a duty cycle in the range of 40 to 60 percent of one period of the clock cycle (TCYCLE). In addition, within the output clock signal pair C/C#, the time between the rising edges of the output clock signal C and the rising edges of the complementary clock signal C# is typically required to be in the range of 45 to 55 percent of TCYCLE. Hence, it is possible for the output clock signal C and the complementary output clock signal C# to have a logic ‘1’ state for up to 15 percent of the period TCYCLE. In this case, a pulse filter capable of filtering a pulse width greater than 0.15×TCYCLE is required to ensure that the clock signal C and the complementary clock signal C# are not simultaneously detected in a logic ‘1’ state. Failure to filter in this manner would result in the system erroneously providing the input clock signal K/K# as the internally selected clock signal EC/EC#.
Given the above-described clock specifications, it is possible for the erroneous logic ‘1’ pulses of clock pulse signal CPULSE to be separated in time by 40% of the period TCYCLE or more. Thus, the pulse filter is also required to filter pulses having a separation greater than or equal to 0.4×TCYCLE. Failure to filter in this manner would result in the system erroneously providing the input clock signal K/K# as the internally selected clock signal EC/EC#.
FIG. 3 is a circuit diagram of a conventional circuit 300 for solving the above-identified problems. Circuit 300 adds delay chain 301 and logical AND gate 302 between the logical AND gate 101 and the multiplexer 102 of FIG. 1. One input of AND gate 302 is coupled to receive the clock pulse signal CPULSE, and the other input of AND gate 302 is coupled to receive a delayed clock pulse signal CPULSE—D, which is a delayed version of the clock pulse signal CPULSE. The delayed clock pulse signal CPULSE—D is created by routing the clock pulse signal CPULSE through delay chain 301. AND gate 302 provides a clock select signal SELK in response to the CPULSE and CPULSE—D signals. In order for circuit 300 to operate without providing undesired glitches in the clock select signal SELK, delay circuit 301 must introduce a delay (TDELAY) with a duration greater than 0.15×TCYCLE and less than 0.4×TCYCLE. The delay TDELAY must have a duration greater than 0.15×TCYCLE to prevent short glitches in the clock pulse signal CPULSE (as illustrated by the logic ‘1’ states of the CPULSE signal in FIG. 2) from being transmitted to the clock select signal SELK. The delay TDELAY must also have a duration less than 0.4×TCYCLE to ensure that a logic ‘1’ glitch in the delayed clock pulse signal CPULSE—D is no longer being provided to AND gate 302 at the same time that a current glitch in the clock pulse signal CPULSE may exist. That is, a delay TDELAY having a duration less than 0.4×TCYCLE prevents the delayed version of a first glitch in the CPULSE signal from interacting with a subsequent glitch in the CPULSE signal.
The limited range of acceptable delays within delay chain 301 has several disadvantages. First, circuit 300 will only work in a frequency range of 0.15/TDELAY (minimum frequency) to 0.4/TDELAY (maximum frequency). Second, the delay introduced by delay chain 301 will vary with voltage, temperature and process, thereby narrowing the frequency range even further. For example, if the maximum delay is equal to 1.5 times the minimum delay (due to voltage, temperature and process variations), and the highest frequency of operation is equal to 250 MHz, then the lowest frequency of operation is limited to 250 MHz×1.5×0.15/0.4=141 MHz.
While there are circuit modifications that can alleviate this problem (e.g., using analog techniques to get a relatively constant delay TDELAY; using an unsymmetrical delay circuit that delays a logic ‘1’ signal much more than a logic ‘0’ signal), these circuit modifications will not eliminate the frequency dependency problem altogether.
It would therefore be desirable to have an output clock selection circuit that overcomes the above-described deficiencies.